{ { { ? { { { ? absolute maximum ratings symbol parameter value units v dss drain to source voltage 60 v i d continuous drain current(@t c = 25 c) 23 a continuous drain current(@t c = 100 c) 15 a i dm drain current pulsed (note 1) 92 a v gs gate to source voltage 20 v e as single pulsed avalanche energy (note 2) 430 mj dv/dt peak diode recovery dv/dt (note 3) 7.0 v/ns p d total power dissipation(@t a = 25 c) 2.5 w total power dissipation(@t c = 25 c) derating factor above 25 c 44 w 0.35 w/c t stg, t j operating junction temperature & storage temperature - 55 ~ 150 c t l maximum lead temperature for soldering purpose, 1/8 from case for 5 seconds. 300 c thermal characteristics symbol parameter value units min. typ. max. r jc thermal resistance, junction-to-case - - 2.85 c/w r ja thermal resistance, junction-to-ambient - - 110 c/w SFD30N06 december, 2002. rev. 0. 1/7 features low r ds (on) (0.04 ? )@v gs =10v gate charge (typical 27nc) improved dv/dt capability 100% avalanche tested maximum junction temperature range (150c) general description this power mosfet is produced using semiwell?s advanced planar stripe, dmos technology. this latest technology has been especially designed to minimize on-state resistance, have a low gate charge with superior sw itching performance, and rugged avalanche characteristics. this power mosfet is well suited for synchronous dc-dc converters and power management in portable and battery operated products. n-channel mosfet semiwell semiconductor symbol 2. drain 3. source 1. gate copyright@semiwell semiconductor co., ltd., all rights reserved. preliminary d-pack (to-252) 1 2 3
SFD30N06 electrical characteristics ( t c = 25 c unless otherwise noted ) symbol parameter test conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0v, i d = 250ua 60 - - v bv dss / t j breakdown voltage temperature coefficient i d = 250ua, referenced to 25 c - 0.062 - v/c i dss zero gate voltage drain current v ds = 60v, v gs = 0v --1ua v ds = 48v, t c = 150 c --10ua i gss gate-source leakage, forward v gs = 20v, v ds = 0v 100 na gate-source leakage, reverse v gs = -20v, v ds = 0v - - -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250ua 2.0 - 4.0 v r ds(on) static drain-source on-state resis- tance v gs =10 v, i d = 11.5a - 0.029 0.04 ? dynamic characteristics c iss input capacitance v gs =0 v, v ds =25v, f = 1mhz - 930 1210 pf c oss output capacitance - 290 380 c rss reverse transfer capacitance - 75 100 dynamic characteristics t d(on) turn-on delay time v dd =30v, i d =15a, r g =50 ? see fig. 13. (note 4, 5) -1540 ns t r rise time - 25 60 t d(off) turn-off delay time - 60 130 t f fall time - 40 90 q g total gate charge v ds =48v, v gs =10v, i d =30a see fig. 12. (note 4, 5) -2735 nc q gs gate-source charge - 6.2 - q gd gate-drain charge(miller charge) - 11.1 - source-drain diode rati ngs and characteristics symbol parameter test cond itions min. typ. max. unit. i s continuous source current integral reverse p-n junction diode in the mosfet --23 a i sm pulsed source current - - 92 v sd diode forward voltage i s =23a, v gs =0v - - 1.5 v t rr reverse recovery time i s =30a,v gs =0v,di f /dt=100a/us -45-ns q rr reverse recovery charge - 65 - nc notes 1. repeativity rating : pulse width limited by junction temperature 2. l = 950uh, i as =23a, v dd = 25v, r g = 0 ? , starting t j = 25c 3. isd 30a, di/dt 300a/us, v dd bv dss , starting t j = 25c 4. pulse test : pulse width 300us, duty cycle 2% 5. essentially independent of operating temperature. 2/7 copyright@semiwell semiconductor co., ltd., all rights reserved.
0.40.60.81.01.21.41.6 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s pulse test 25 i dr [a], reverse drain current v sd [v], source-drain voltage 246810 10 0 10 1 150 o c 25 o c -55 o c notes : 1. v ds = 25v 2. 250 s pulse test i d , drain current [a] v gs , gate-source voltage [v] 10 -1 10 0 10 1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.0 v 5.5 v bottom : 5.0 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] 0 5 10 15 20 25 30 0 2 4 6 8 10 12 v ds = 30v v ds = 48v note : i d = 30.0 a v gs , gate-source voltage [v] q g , total gate charge [nc] 0 20 40 60 80 100 120 140 0 20 40 60 80 100 v gs = 20v v gs = 10v note : t j = 25 r ds(on) , drain-source on-resistance[m ? ] i d , drain current [a] 3/7 fig 3. on resistance variation vs. drain current and gate voltage fig 4. on state current vs. allowable case temperature fig 5. capacitance characteristics fig 6. gate charge characteristics SFD30N06 fig 1. on-state characteristics fig 2. transfer characteristics copyright@semiwell semiconductor co., ltd., all rights reserved. 0 5 10 15 20 25 30 35 0 500 1000 1500 2000 c rss c oss c iss notes : 1. v gs = 0v 2. f=1mhz c iss =c gs +c gd (c ds =shorted) c oss =c ds +c gd c rss =c gd capacitance [pf] v ds , drain-source voltage [v]
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -2 10 -1 10 0 n otes : 1. z jc (t) = 2.85 /w max. 2. d uty factor, d =t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), thermal response t 1 , square w ave pulse d uration [sec] 25 50 75 100 125 150 0 5 10 15 20 25 i d' drain current [a] t c' case temperature [ o c] 10 -1 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 10 3 dc 10 ms 1 ms 100 s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 notes : 1. v gs = 10 v 2. i d = 11.5 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] fig 9. maximum safe operating area fig 10. maximum drain current vs. case temperature fig 11. transient thermal response curve fig 7. breakdown voltage variation vs. junction temperature fig 8. on-resistance variation vs. junction temperature SFD30N06 4/7 copyright@semiwell semiconductor co., ltd., all rights reserved.
5/7 fig 13. switching time test circuit & waveforms fig 14. unclamped inductive swit ching test circuit & waveforms SFD30N06 fig. 12. gate charge test circuit & waveforms e as =l l i as 2 ---- 2 1 -------------------- bv dss -- v dd bv dss e as =l l i as 2 ---- 2 1 e as =l l i as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -- v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d charge v gs 10v q g q gs q gd 1ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd charge v gs 10v q g q gs q gd 1ma v gs dut v ds 300nf 50k 200nf 12v same type as dut v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd ( 0.5 rated v ds ) 10 v v ds r l dut pulse generator v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd ( 0.5 rated v ds ) v v ds r l dut pulse generator r g v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd ( 0.5 rated v ds ) 10 v v ds r l dut pulse generator v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v in v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd ( 0.5 rated v ds ) v v ds r l dut pulse generator r g copyright@semiwell semiconductor co., ltd., all rights reserved.
SFD30N06 dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i s controlled by pulse period v dd l l i s i s fig. 15. peak diode recovery dv/dt test circuit & waveforms 10v v gs ( driver ) i s ( dut ) v ds ( dut ) v dd body diode forward voltage drop v f i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- 10v v gs ( driver ) i s ( dut ) v ds ( dut ) v dd body diode forward voltage drop v f i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period -------------------------- 6/7 copyright@semiwell semiconductor co., ltd., all rights reserved.
dim. mm inch min. typ. max. min. typ. max. a 6.48 6.604 6.73 0.255 0.26 0.265 b 5.0 5.08 5.21 0.197 0.2 0.205 c 7.42 7.8 8.18 0.292 0.307 0.322 d 2.184 2.286 2.388 0.086 0.09 0.094 e 0.762 0.813 0.864 0.03 0.032 0.034 f 1.016 1.067 1.118 0.04 0.042 0.044 g 2.286 0.09 h 2.286 0.09 i 0.534 0.61 0.686 0.021 0.024 0.027 j 1.016 1.067 1.118 0.04 0.042 0.044 k 0.508 0.02 l 0.762 0.03 1.57 0.06 SFD30N06 to-252(d-pak) package dimension 7/7 1. gate 2. drain 3. source a b c d e g f 3 2 1 h i j k l copyright@semiwell semiconductor co., ltd., all rights reserved.
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